3．Characteristics of Reduced Instruction Set Architectures
Although a variety of different approaches to reduced instruction set architecture have been taken，certain characteristics are common to all of them．These characteristics are listed in Table 2．1 and described here．
The first characteristic listed in Table 2．1 is that there is one machine instruction per machine cycle．A machine cycle is defined to be the time it takes to fetch two operands from registers，perform an ALU operation，and store the result in a register．Thus，RISC machine instructions should be no more complicated than，and execute about as fast as，microinxtructions on CISC machines．[3] With simple，one –cycle instructions，there is little or no need for microcode；the machine instructions can be hardwired[4]．Such instructions should execute faster than comparable machine instructions on other machines，since it is not necessary to access a microprogram control store during instruction execution．
A second characteristic is that most operations should be register-to-register，with only simple LOAD and STORE operations accessing memory．This design feature simplifies the instruction set and therefore the control unit．For example，a RISC instruction set may include only one or two ADD instructions（e. g. ，integer add，add with carry）；the VAX has 25 different ADD instructions．Another benefit is that such an architecture encourages the optimization of register use，so that frequently accessed operands remain in high-speed storage．
Returning to Table 2-1，a third characteristic is the use of simple addressing modes．Almost all instructions use simple register addressing．Several additional modes，such as displacement and PC-relative，may be included．Other，more complex modes can be synthesized in software from the simple ones．Again，this design feature simplifies the instruction set and the control unit．
A final common characteristic is the use of simple instruction formats．Generally，only one or a few formats are used．Instruction length is fixed and aligned on word boundaries．Field locations，especially the opcode，are fixed．This design feature has a number of benefits．With fixed fields，opcode decoding and register operand accessing can occur simultaneously．Simplified formats simplify the control unit．Instruction fetching is optimized since word-length units are fetched．This also means that a single instruction does not cross page boundaries．
NOTES
[1] lend itself to适合于…
[2] register file寄存器组，作为数据或指令的临时存放处的一种多位寄存器组，有时称作栈。
[3] 此句为比较结构no more... than…，中间插入并列句将被比较对象隔开了。
[4] hardwired硬连线的，即机器指令是固化在硬件（芯片）上的。
KEYWORDS
instruction set 指令系统，指令集
reduced instruction set computer（RISC） 精简指令系统计算机
pipeline 流水线
operand 操作数
register 寄存器
compiler 编译器，编译程序
branch instruction 转移指令，分支指令 |
